| [384] | 1 | /*-
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| 2 | * Copyright (c) 2010, 2011 Rick van der Zwet <info@rickvanderzwet.nl>
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| 3 | *
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| 4 | * Permission to use, copy, modify, and distribute this software for any
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| 5 | * purpose with or without fee is hereby granted, provided that the above
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| 6 | * copyright notice and this permission notice appear in all copies.
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| 7 | *
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| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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| 15 | */
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| 16 |
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| 17 | /*-
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| 18 | * Copyright (c) 2001-2003, Shunsuke Akiyama <akiyama@FreeBSD.org>.
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| 19 | * All rights reserved.
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| 20 | *
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| 21 | * Redistribution and use in source and binary forms, with or without
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| 22 | * modification, are permitted provided that the following conditions
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| 23 | * are met:
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| 24 | * 1. Redistributions of source code must retain the above copyright
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| 25 | * notice, this list of conditions and the following disclaimer.
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| 26 | * 2. Redistributions in binary form must reproduce the above copyright
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| 27 | * notice, this list of conditions and the following disclaimer in the
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| 28 | * documentation and/or other materials provided with the distribution.
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| 29 | *
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| 30 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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| 31 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| 32 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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| 33 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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| 34 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 35 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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| 36 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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| 37 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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| 38 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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| 39 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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| 40 | * SUCH DAMAGE.
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| 41 | *
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| 42 | * $FreeBSD: release/10.1.0/sys/dev/usb/net/if_rtlreg.h 215335 2010-11-15 06:04:25Z kevlo $
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| 43 | */
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| 44 |
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| 45 | #define RTL_CONFIG_IDX 0 /* config number 1 */
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| 46 | #define RTL_IFACE_IDX 0
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| 47 |
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| 48 | #define RTL_INTR_PKTLEN 0x8
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| 49 |
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| 50 | #define RTL_TIMEOUT 50
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| 51 | #define RTL_MIN_FRAMELEN 60
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| 52 |
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| 53 | /* Registers. */
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| 54 | #define RTL_IDR0 0x0120
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| 55 | #define RTL_IDR1 0x0121
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| 56 | #define RTL_IDR2 0x0122
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| 57 | #define RTL_IDR3 0x0123
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| 58 | #define RTL_IDR4 0x0124
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| 59 | #define RTL_IDR5 0x0125
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| 60 |
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| 61 | #define RTL_MAR0 0x0126
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| 62 | #define RTL_MAR1 0x0127
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| 63 | #define RTL_MAR2 0x0128
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| 64 | #define RTL_MAR3 0x0129
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| 65 | #define RTL_MAR4 0x012A
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| 66 | #define RTL_MAR5 0x012B
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| 67 | #define RTL_MAR6 0x012C
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| 68 | #define RTL_MAR7 0x012D
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| 69 |
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| 70 | #define RTL_CR 0x012E /* B, R/W */
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| 71 | #define RTL_CR_SOFT_RST 0x10
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| 72 | #define RTL_CR_RE 0x08
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| 73 | #define RTL_CR_TE 0x04
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| 74 | #define RTL_CR_EP3CLREN 0x02
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| 75 |
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| 76 | #define RTL_TCR 0x012F /* B, R/W */
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| 77 | #define RTL_TCR_TXRR1 0x80
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| 78 | #define RTL_TCR_TXRR0 0x40
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| 79 | #define RTL_TCR_IFG1 0x10
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| 80 | #define RTL_TCR_IFG0 0x08
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| 81 | #define RTL_TCR_NOCRC 0x01
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| 82 | #define RTL_TCR_CONFIG (RTL_TCR_TXRR1 | RTL_TCR_TXRR0 | \
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| 83 | RTL_TCR_IFG1 | RTL_TCR_IFG0)
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| 84 |
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| 85 | #define RTL_RCR 0x0130 /* W, R/W */
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| 86 | #define RTL_RCR_TAIL 0x80
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| 87 | #define RTL_RCR_AER 0x40
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| 88 | #define RTL_RCR_AR 0x20
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| 89 | #define RTL_RCR_AM 0x10
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| 90 | #define RTL_RCR_AB 0x08
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| 91 | #define RTL_RCR_AD 0x04
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| 92 | #define RTL_RCR_AAM 0x02
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| 93 | #define RTL_RCR_AAP 0x01
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| 94 | #define RTL_RCR_CONFIG (RTL_RCR_TAIL | RTL_RCR_AD)
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| 95 |
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| 96 | #define RTL_TSR 0x0132
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| 97 | #define RTL_RSR 0x0133
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| 98 | #define RTL_CON0 0x0135
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| 99 | #define RTL_CON1 0x0136
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| 100 | #define RTL_MSR 0x0137
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| 101 | #define RTL_PHYADD 0x0138
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| 102 | #define RTL_PHYDAT 0x0139
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| 103 |
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| 104 | #define RTL_PHYCNT 0x013B /* B, R/W */
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| 105 | #define RTL_PHYCNT_PHYOWN 0x40
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| 106 | #define RTL_PHYCNT_RWCR 0x20
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| 107 |
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| 108 | #define RTL_GPPC 0x013D
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| 109 | #define RTL_WAKECNT 0x013E
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| 110 |
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| 111 | #define RTL_BMCR 0x0140
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| 112 | #define RTL_BMCR_SPD_SET 0x2000
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| 113 | #define RTL_BMCR_DUPLEX 0x0100
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| 114 |
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| 115 | #define RTL_BMSR 0x0142
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| 116 |
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| 117 | #define RTL_ANAR 0x0144 /* W, R/W */
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| 118 | #define RTL_ANAR_PAUSE 0x0400
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| 119 |
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| 120 | #define RTL_ANLP 0x0146 /* W, R/O */
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| 121 | #define RTL_ANLP_PAUSE 0x0400
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| 122 |
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| 123 | #define RTL_AER 0x0148
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| 124 |
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| 125 | #define RTL_NWAYT 0x014A
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| 126 | #define RTL_CSCR 0x014C
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| 127 |
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| 128 | #define RTL_CRC0 0x014E
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| 129 | #define RTL_CRC1 0x0150
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| 130 | #define RTL_CRC2 0x0152
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| 131 | #define RTL_CRC3 0x0154
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| 132 | #define RTL_CRC4 0x0156
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| 133 |
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| 134 | #define RTL_BYTEMASK0 0x0158
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| 135 | #define RTL_BYTEMASK1 0x0160
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| 136 | #define RTL_BYTEMASK2 0x0168
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| 137 | #define RTL_BYTEMASK3 0x0170
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| 138 | #define RTL_BYTEMASK4 0x0178
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| 139 |
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| 140 | #define RTL_PHY1 0x0180
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| 141 | #define RTL_PHY2 0x0184
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| 142 |
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| 143 | #define RTL_TW1 0x0186
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| 144 |
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| 145 | #define RTL_REG_MIN 0x0120
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| 146 | #define RTL_REG_MAX 0x0189
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| 147 |
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| 148 | /* EEPROM address declarations. */
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| 149 | #define RTL_EEPROM_BASE 0x1200
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| 150 | #define RTL_EEPROM_IDR0 (RTL_EEPROM_BASE + 0x02)
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| 151 | #define RTL_EEPROM_IDR1 (RTL_EEPROM_BASE + 0x03)
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| 152 | #define RTL_EEPROM_IDR2 (RTL_EEPROM_BASE + 0x03)
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| 153 | #define RTL_EEPROM_IDR3 (RTL_EEPROM_BASE + 0x03)
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| 154 | #define RTL_EEPROM_IDR4 (RTL_EEPROM_BASE + 0x03)
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| 155 | #define RTL_EEPROM_IDR5 (RTL_EEPROM_BASE + 0x03)
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| 156 | #define RTL_EEPROM_INTERVAL (RTL_EEPROM_BASE + 0x17)
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| 157 |
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| 158 | #define RTL_RXSTAT_VALID (0x01 << 12)
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| 159 | #define RTL_RXSTAT_RUNT (0x02 << 12)
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| 160 | #define RTL_RXSTAT_PMATCH (0x04 << 12)
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| 161 | #define RTL_RXSTAT_MCAST (0x08 << 12)
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| 162 |
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| 163 | /* New entries (imported from r8152.c) */
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| 164 | #define R8152_PHY_ID 32
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| 165 |
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| 166 | #define PLA_IDR 0xc000
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| 167 | #define PLA_RCR 0xc010
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| 168 | #define PLA_RMS 0xc016
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| 169 | #define PLA_RXFIFO_CTRL0 0xc0a0
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| 170 | #define PLA_RXFIFO_CTRL1 0xc0a4
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| 171 | #define PLA_RXFIFO_CTRL2 0xc0a8
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| 172 | #define PLA_FMC 0xc0b4
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| 173 | #define PLA_CFG_WOL 0xc0b6
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| 174 | #define PLA_TEREDO_CFG 0xc0bc
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| 175 | #define PLA_MAR 0xcd00
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| 176 | #define PLA_BACKUP 0xd000
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| 177 | #define PAL_BDC_CR 0xd1a0
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| 178 | #define PLA_TEREDO_TIMER 0xd2cc
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| 179 | #define PLA_REALWOW_TIMER 0xd2e8
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| 180 | #define PLA_LEDSEL 0xdd90
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| 181 | #define PLA_LED_FEATURE 0xdd92
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| 182 | #define PLA_PHYAR 0xde00
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| 183 | #define PLA_BOOT_CTRL 0xe004
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| 184 | #define PLA_GPHY_INTR_IMR 0xe022
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| 185 | #define PLA_EEE_CR 0xe040
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| 186 | #define PLA_EEEP_CR 0xe080
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| 187 | #define PLA_MAC_PWR_CTRL 0xe0c0
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| 188 | #define PLA_MAC_PWR_CTRL2 0xe0ca
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| 189 | #define PLA_MAC_PWR_CTRL3 0xe0cc
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| 190 | #define PLA_MAC_PWR_CTRL4 0xe0ce
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| 191 | #define PLA_WDT6_CTRL 0xe428
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| 192 | #define PLA_TCR0 0xe610
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| 193 | #define PLA_TCR1 0xe612
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| 194 | #define PLA_MTPS 0xe615
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| 195 | #define PLA_TXFIFO_CTRL 0xe618
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| 196 | #define PLA_RSTTALLY 0xe800
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| 197 | #define PLA_CR 0xe813
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| 198 | #define PLA_CRWECR 0xe81c
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| 199 | #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
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| 200 | #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
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| 201 | #define PLA_CONFIG5 0xe822
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| 202 | #define PLA_PHY_PWR 0xe84c
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| 203 | #define PLA_OOB_CTRL 0xe84f
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| 204 | #define PLA_CPCR 0xe854
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| 205 | #define PLA_MISC_0 0xe858
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| 206 | #define PLA_MISC_1 0xe85a
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| 207 | #define PLA_OCP_GPHY_BASE 0xe86c
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| 208 | #define PLA_TALLYCNT 0xe890
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| 209 | #define PLA_SFF_STS_7 0xe8de
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| 210 | #define PLA_PHYSTATUS 0xe908
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| 211 | #define PLA_BP_BA 0xfc26
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| 212 | #define PLA_BP_0 0xfc28
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| 213 | #define PLA_BP_1 0xfc2a
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| 214 | #define PLA_BP_2 0xfc2c
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| 215 | #define PLA_BP_3 0xfc2e
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| 216 | #define PLA_BP_4 0xfc30
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| 217 | #define PLA_BP_5 0xfc32
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| 218 | #define PLA_BP_6 0xfc34
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| 219 | #define PLA_BP_7 0xfc36
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| 220 | #define PLA_BP_EN 0xfc38
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| 221 |
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| 222 | #define USB_U2P3_CTRL 0xb460
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| 223 | #define USB_DEV_STAT 0xb808
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| 224 | #define USB_USB_CTRL 0xd406
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| 225 | #define USB_PHY_CTRL 0xd408
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| 226 | #define USB_TX_AGG 0xd40a
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| 227 | #define USB_RX_BUF_TH 0xd40c
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| 228 | #define USB_USB_TIMER 0xd428
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| 229 | #define USB_RX_EARLY_AGG 0xd42c
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| 230 | #define USB_PM_CTRL_STATUS 0xd432
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| 231 | #define USB_TX_DMA 0xd434
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| 232 | #define USB_TOLERANCE 0xd490
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| 233 | #define USB_LPM_CTRL 0xd41a
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| 234 | #define USB_UPS_CTRL 0xd800
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| 235 | #define USB_MISC_0 0xd81a
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| 236 | #define USB_POWER_CUT 0xd80a
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| 237 | #define USB_AFE_CTRL2 0xd824
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| 238 | #define USB_WDT11_CTRL 0xe43c
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| 239 | #define USB_BP_BA 0xfc26
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| 240 | #define USB_BP_0 0xfc28
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| 241 | #define USB_BP_1 0xfc2a
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| 242 | #define USB_BP_2 0xfc2c
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| 243 | #define USB_BP_3 0xfc2e
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| 244 | #define USB_BP_4 0xfc30
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| 245 | #define USB_BP_5 0xfc32
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| 246 | #define USB_BP_6 0xfc34
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| 247 | #define USB_BP_7 0xfc36
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| 248 | #define USB_BP_EN 0xfc38
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| 249 |
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| 250 | /* OCP Registers */
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| 251 | #define OCP_ALDPS_CONFIG 0x2010
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| 252 | #define OCP_EEE_CONFIG1 0x2080
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| 253 | #define OCP_EEE_CONFIG2 0x2092
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| 254 | #define OCP_EEE_CONFIG3 0x2094
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| 255 | #define OCP_BASE_MII 0xa400
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| 256 | #define OCP_EEE_AR 0xa41a
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| 257 | #define OCP_EEE_DATA 0xa41c
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| 258 | #define OCP_PHY_STATUS 0xa420
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| 259 | #define OCP_POWER_CFG 0xa430
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| 260 | #define OCP_EEE_CFG 0xa432
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| 261 | #define OCP_SRAM_ADDR 0xa436
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| 262 | #define OCP_SRAM_DATA 0xa438
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| 263 | #define OCP_DOWN_SPEED 0xa442
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| 264 | #define OCP_EEE_ABLE 0xa5c4
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| 265 | #define OCP_EEE_ADV 0xa5d0
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| 266 | #define OCP_EEE_LPABLE 0xa5d2
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| 267 | #define OCP_ADC_CFG 0xbc06
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| 268 |
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| 269 | /* SRAM Register */
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| 270 | #define SRAM_LPF_CFG 0x8012
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| 271 | #define SRAM_10M_AMP1 0x8080
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| 272 | #define SRAM_10M_AMP2 0x8082
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| 273 | #define SRAM_IMPEDANCE 0x8084
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| 274 |
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| 275 | /* PLA_RCR */
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| 276 | #define RCR_AAP 0x00000001
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| 277 | #define RCR_APM 0x00000002
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| 278 | #define RCR_AM 0x00000004
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| 279 | #define RCR_AB 0x00000008
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| 280 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
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| 281 |
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| 282 | /* PLA_RXFIFO_CTRL0 */
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| 283 | #define RXFIFO_THR1_NORMAL 0x00080002
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| 284 | #define RXFIFO_THR1_OOB 0x01800003
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| 285 |
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| 286 | /* PLA_RXFIFO_CTRL1 */
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| 287 | #define RXFIFO_THR2_FULL 0x00000060
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| 288 | #define RXFIFO_THR2_HIGH 0x00000038
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| 289 | #define RXFIFO_THR2_OOB 0x0000004a
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| 290 | #define RXFIFO_THR2_NORMAL 0x00a0
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| 291 |
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| 292 | /* PLA_RXFIFO_CTRL2 */
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| 293 | #define RXFIFO_THR3_FULL 0x00000078
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| 294 | #define RXFIFO_THR3_HIGH 0x00000048
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| 295 | #define RXFIFO_THR3_OOB 0x0000005a
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| 296 | #define RXFIFO_THR3_NORMAL 0x0110
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| 297 |
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| 298 | /* PLA_TXFIFO_CTRL */
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| 299 | #define TXFIFO_THR_NORMAL 0x00400008
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| 300 | #define TXFIFO_THR_NORMAL2 0x01000008
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| 301 |
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| 302 | /* PLA_FMC */
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| 303 | #define FMC_FCR_MCU_EN 0x0001
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| 304 |
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| 305 | /* PLA_EEEP_CR */
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| 306 | #define EEEP_CR_EEEP_TX 0x0002
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| 307 |
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| 308 | /* PLA_WDT6_CTRL */
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| 309 | #define WDT6_SET_MODE 0x0010
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| 310 |
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| 311 | /* PLA_TCR0 */
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| 312 | #define TCR0_TX_EMPTY 0x0800
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| 313 | #define TCR0_AUTO_FIFO 0x0080
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| 314 |
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| 315 | /* PLA_TCR1 */
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| 316 | #define VERSION_MASK 0x7cf0
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| 317 |
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| 318 | /* PLA_MTPS */
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| 319 | #define MTPS_JUMBO (12 * 1024 / 64)
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| 320 | #define MTPS_DEFAULT (6 * 1024 / 64)
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| 321 |
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| 322 | /* PLA_RSTTALLY */
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| 323 | #define TALLY_RESET 0x0001
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| 324 |
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| 325 | /* PLA_CR */
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| 326 | #define CR_RST 0x10
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| 327 | #define CR_RE 0x08
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| 328 | #define CR_TE 0x04
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| 329 |
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| 330 | /* PLA_CRWECR */
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| 331 | #define CRWECR_NORAML 0x00
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| 332 | #define CRWECR_CONFIG 0xc0
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| 333 |
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| 334 | /* PLA_OOB_CTRL */
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| 335 | #define NOW_IS_OOB 0x80
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| 336 | #define TXFIFO_EMPTY 0x20
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| 337 | #define RXFIFO_EMPTY 0x10
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| 338 | #define LINK_LIST_READY 0x02
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| 339 | #define DIS_MCU_CLROOB 0x01
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| 340 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
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| 341 |
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| 342 | /* PLA_MISC_1 */
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| 343 | #define RXDY_GATED_EN 0x0008
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| 344 |
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| 345 | /* PLA_SFF_STS_7 */
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| 346 | #define RE_INIT_LL 0x8000
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| 347 | #define MCU_BORW_EN 0x4000
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| 348 |
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| 349 | /* PLA_CPCR */
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| 350 | #define CPCR_RX_VLAN 0x0040
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| 351 |
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| 352 | /* PLA_CFG_WOL */
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| 353 | #define MAGIC_EN 0x0001
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| 354 |
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| 355 | /* PLA_TEREDO_CFG */
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| 356 | #define TEREDO_SEL 0x8000
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| 357 | #define TEREDO_WAKE_MASK 0x7f00
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| 358 | #define TEREDO_RS_EVENT_MASK 0x00fe
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| 359 | #define OOB_TEREDO_EN 0x0001
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| 360 |
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| 361 | /* PAL_BDC_CR */
|
|---|
| 362 | #define ALDPS_PROXY_MODE 0x0001
|
|---|
| 363 |
|
|---|
| 364 | /* PLA_CONFIG34 */
|
|---|
| 365 | #define LINK_ON_WAKE_EN 0x0010
|
|---|
| 366 | #define LINK_OFF_WAKE_EN 0x0008
|
|---|
| 367 |
|
|---|
| 368 | /* PLA_CONFIG5 */
|
|---|
| 369 | #define BWF_EN 0x0040
|
|---|
| 370 | #define MWF_EN 0x0020
|
|---|
| 371 | #define UWF_EN 0x0010
|
|---|
| 372 | #define LAN_WAKE_EN 0x0002
|
|---|
| 373 |
|
|---|
| 374 | /* PLA_LED_FEATURE */
|
|---|
| 375 | #define LED_MODE_MASK 0x0700
|
|---|
| 376 |
|
|---|
| 377 | /* PLA_PHY_PWR */
|
|---|
| 378 | #define TX_10M_IDLE_EN 0x0080
|
|---|
| 379 | #define PFM_PWM_SWITCH 0x0040
|
|---|
| 380 |
|
|---|
| 381 | /* PLA_MAC_PWR_CTRL */
|
|---|
| 382 | #define D3_CLK_GATED_EN 0x00004000
|
|---|
| 383 | #define MCU_CLK_RATIO 0x07010f07
|
|---|
| 384 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
|
|---|
| 385 | #define ALDPS_SPDWN_RATIO 0x0f87
|
|---|
| 386 |
|
|---|
| 387 | /* PLA_MAC_PWR_CTRL2 */
|
|---|
| 388 | #define EEE_SPDWN_RATIO 0x8007
|
|---|
| 389 |
|
|---|
| 390 | /* PLA_MAC_PWR_CTRL3 */
|
|---|
| 391 | #define PKT_AVAIL_SPDWN_EN 0x0100
|
|---|
| 392 | #define SUSPEND_SPDWN_EN 0x0004
|
|---|
| 393 | #define U1U2_SPDWN_EN 0x0002
|
|---|
| 394 | #define L1_SPDWN_EN 0x0001
|
|---|
| 395 |
|
|---|
| 396 | /* PLA_MAC_PWR_CTRL4 */
|
|---|
| 397 | #define PWRSAVE_SPDWN_EN 0x1000
|
|---|
| 398 | #define RXDV_SPDWN_EN 0x0800
|
|---|
| 399 | #define TX10MIDLE_EN 0x0100
|
|---|
| 400 | #define TP100_SPDWN_EN 0x0020
|
|---|
| 401 | #define TP500_SPDWN_EN 0x0010
|
|---|
| 402 | #define TP1000_SPDWN_EN 0x0008
|
|---|
| 403 | #define EEE_SPDWN_EN 0x0001
|
|---|
| 404 |
|
|---|
| 405 | /* PLA_GPHY_INTR_IMR */
|
|---|
| 406 | #define GPHY_STS_MSK 0x0001
|
|---|
| 407 | #define SPEED_DOWN_MSK 0x0002
|
|---|
| 408 | #define SPDWN_RXDV_MSK 0x0004
|
|---|
| 409 | #define SPDWN_LINKCHG_MSK 0x0008
|
|---|
| 410 |
|
|---|
| 411 | /* PLA_PHYAR */
|
|---|
| 412 | #define PHYAR_FLAG 0x80000000
|
|---|
| 413 |
|
|---|
| 414 | /* PLA_EEE_CR */
|
|---|
| 415 | #define EEE_RX_EN 0x0001
|
|---|
| 416 | #define EEE_TX_EN 0x0002
|
|---|
| 417 |
|
|---|
| 418 | /* PLA_BOOT_CTRL */
|
|---|
| 419 | #define AUTOLOAD_DONE 0x0002
|
|---|
| 420 |
|
|---|
| 421 | /* USB_DEV_STAT */
|
|---|
| 422 | #define STAT_SPEED_MASK 0x0006
|
|---|
| 423 | #define STAT_SPEED_HIGH 0x0000
|
|---|
| 424 | #define STAT_SPEED_FULL 0x0002
|
|---|
| 425 |
|
|---|
| 426 | /* USB_TX_AGG */
|
|---|
| 427 | #define TX_AGG_MAX_THRESHOLD 0x03
|
|---|
| 428 |
|
|---|
| 429 | /* USB_RX_BUF_TH */
|
|---|
| 430 | #define RX_THR_SUPPER 0x0c350180
|
|---|
| 431 | #define RX_THR_HIGH 0x7a120180
|
|---|
| 432 | #define RX_THR_SLOW 0xffff0180
|
|---|
| 433 |
|
|---|
| 434 | /* USB_TX_DMA */
|
|---|
| 435 | #define TEST_MODE_DISABLE 0x00000001
|
|---|
| 436 | #define TX_SIZE_ADJUST1 0x00000100
|
|---|
| 437 |
|
|---|
| 438 | /* USB_UPS_CTRL */
|
|---|
| 439 | #define POWER_CUT 0x0100
|
|---|
| 440 |
|
|---|
| 441 | /* USB_PM_CTRL_STATUS */
|
|---|
| 442 | #define RESUME_INDICATE 0x0001
|
|---|
| 443 |
|
|---|
| 444 | /* USB_USB_CTRL */
|
|---|
| 445 | #define RX_AGG_DISABLE 0x0010
|
|---|
| 446 |
|
|---|
| 447 | /* USB_U2P3_CTRL */
|
|---|
| 448 | #define U2P3_ENABLE 0x0001
|
|---|
| 449 |
|
|---|
| 450 | /* USB_POWER_CUT */
|
|---|
| 451 | #define PWR_EN 0x0001
|
|---|
| 452 | #define PHASE2_EN 0x0008
|
|---|
| 453 |
|
|---|
| 454 | /* USB_MISC_0 */
|
|---|
| 455 | #define PCUT_STATUS 0x0001
|
|---|
| 456 |
|
|---|
| 457 | /* USB_RX_EARLY_AGG */
|
|---|
| 458 | #define EARLY_AGG_SUPPER 0x0e832981
|
|---|
| 459 | #define EARLY_AGG_HIGH 0x0e837a12
|
|---|
| 460 | #define EARLY_AGG_SLOW 0x0e83ffff
|
|---|
| 461 |
|
|---|
| 462 | /* USB_WDT11_CTRL */
|
|---|
| 463 | #define TIMER11_EN 0x0001
|
|---|
| 464 |
|
|---|
| 465 | /* USB_LPM_CTRL */
|
|---|
| 466 | #define LPM_TIMER_MASK 0x0c
|
|---|
| 467 | #define LPM_TIMER_500MS 0x04 /* 500 ms */
|
|---|
| 468 | #define LPM_TIMER_500US 0x0c /* 500 us */
|
|---|
| 469 |
|
|---|
| 470 | /* USB_AFE_CTRL2 */
|
|---|
| 471 | #define SEN_VAL_MASK 0xf800
|
|---|
| 472 | #define SEN_VAL_NORMAL 0xa000
|
|---|
| 473 | #define SEL_RXIDLE 0x0100
|
|---|
| 474 |
|
|---|
| 475 | /* OCP_ALDPS_CONFIG */
|
|---|
| 476 | #define ENPWRSAVE 0x8000
|
|---|
| 477 | #define ENPDNPS 0x0200
|
|---|
| 478 | #define LINKENA 0x0100
|
|---|
| 479 | #define DIS_SDSAVE 0x0010
|
|---|
| 480 |
|
|---|
| 481 | /* OCP_PHY_STATUS */
|
|---|
| 482 | #define PHY_STAT_MASK 0x0007
|
|---|
| 483 | #define PHY_STAT_LAN_ON 3
|
|---|
| 484 | #define PHY_STAT_PWRDN 5
|
|---|
| 485 |
|
|---|
| 486 | /* OCP_POWER_CFG */
|
|---|
| 487 | #define EEE_CLKDIV_EN 0x8000
|
|---|
| 488 | #define EN_ALDPS 0x0004
|
|---|
| 489 | #define EN_10M_PLLOFF 0x0001
|
|---|
| 490 |
|
|---|
| 491 | /* OCP_EEE_CONFIG1 */
|
|---|
| 492 | #define RG_TXLPI_MSK_HFDUP 0x8000
|
|---|
| 493 | #define RG_MATCLR_EN 0x4000
|
|---|
| 494 | #define EEE_10_CAP 0x2000
|
|---|
| 495 | #define EEE_NWAY_EN 0x1000
|
|---|
| 496 | #define TX_QUIET_EN 0x0200
|
|---|
| 497 | #define RX_QUIET_EN 0x0100
|
|---|
| 498 | #define sd_rise_time_mask 0x0070
|
|---|
| 499 | #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
|
|---|
| 500 | #define RG_RXLPI_MSK_HFDUP 0x0008
|
|---|
| 501 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
|
|---|
| 502 |
|
|---|
| 503 | /* OCP_EEE_CONFIG2 */
|
|---|
| 504 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
|
|---|
| 505 | #define RG_DACQUIET_EN 0x0400
|
|---|
| 506 | #define RG_LDVQUIET_EN 0x0200
|
|---|
| 507 | #define RG_CKRSEL 0x0020
|
|---|
| 508 | #define RG_EEEPRG_EN 0x0010
|
|---|
| 509 |
|
|---|
| 510 | /* OCP_EEE_CONFIG3 */
|
|---|
| 511 | #define fast_snr_mask 0xff80
|
|---|
| 512 | #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
|
|---|
| 513 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
|
|---|
| 514 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */
|
|---|
| 515 |
|
|---|
| 516 | /* OCP_EEE_AR */
|
|---|
| 517 | /* bit[15:14] function */
|
|---|
| 518 | #define FUN_ADDR 0x0000
|
|---|
| 519 | #define FUN_DATA 0x4000
|
|---|
| 520 | /* bit[4:0] device addr */
|
|---|
| 521 |
|
|---|
| 522 | /* OCP_EEE_CFG */
|
|---|
| 523 | #define CTAP_SHORT_EN 0x0040
|
|---|
| 524 | #define EEE10_EN 0x0010
|
|---|
| 525 |
|
|---|
| 526 | /* OCP_DOWN_SPEED */
|
|---|
| 527 | #define EN_10M_BGOFF 0x0080
|
|---|
| 528 |
|
|---|
| 529 | /* OCP_ADC_CFG */
|
|---|
| 530 | #define CKADSEL_L 0x0100
|
|---|
| 531 | #define ADC_EN 0x0080
|
|---|
| 532 | #define EN_EMI_L 0x0040
|
|---|
| 533 |
|
|---|
| 534 | /* SRAM_LPF_CFG */
|
|---|
| 535 | #define LPF_AUTO_TUNE 0x8000
|
|---|
| 536 |
|
|---|
| 537 | /* SRAM_10M_AMP1 */
|
|---|
| 538 | #define GDAC_IB_UPALL 0x0008
|
|---|
| 539 |
|
|---|
| 540 | /* SRAM_10M_AMP2 */
|
|---|
| 541 | #define AMP_DN 0x0200
|
|---|
| 542 |
|
|---|
| 543 | /* SRAM_IMPEDANCE */
|
|---|
| 544 | #define RX_DRIVING_MASK 0x6000
|
|---|
| 545 |
|
|---|
| 546 | enum rtl_register_content {
|
|---|
| 547 | _1000bps = 0x10,
|
|---|
| 548 | _100bps = 0x08,
|
|---|
| 549 | _10bps = 0x04,
|
|---|
| 550 | LINK_STATUS = 0x02,
|
|---|
| 551 | FULL_DUP = 0x01,
|
|---|
| 552 | };
|
|---|
| 553 |
|
|---|
| 554 | #define RTL8152_MAX_TX 4
|
|---|
| 555 | #define RTL8152_MAX_RX 10
|
|---|
| 556 | #define INTBUFSIZE 2
|
|---|
| 557 | #define CRC_SIZE 4
|
|---|
| 558 | #define TX_ALIGN 4
|
|---|
| 559 | #define RX_ALIGN 8
|
|---|
| 560 |
|
|---|
| 561 | #define INTR_LINK 0x0004
|
|---|
| 562 |
|
|---|
| 563 | #define RTL8152_REQT_READ 0xc0
|
|---|
| 564 | #define RTL8152_REQT_WRITE 0x40
|
|---|
| 565 | #define RTL8152_REQ_GET_REGS 0x05
|
|---|
| 566 | #define RTL8152_REQ_SET_REGS 0x05
|
|---|
| 567 |
|
|---|
| 568 | #define BYTE_EN_DWORD 0xff
|
|---|
| 569 | #define BYTE_EN_WORD 0x33
|
|---|
| 570 | #define BYTE_EN_BYTE 0x11
|
|---|
| 571 | #define BYTE_EN_SIX_BYTES 0x3f
|
|---|
| 572 | #define BYTE_EN_START_MASK 0x0f
|
|---|
| 573 | #define BYTE_EN_END_MASK 0xf0
|
|---|
| 574 |
|
|---|
| 575 | #define VLAN_ETH_FRAME_LEN 1518 /* Max. octets in frame sans FCS */
|
|---|
| 576 | #define VLAN_HLEN 4 /* The additional bytes (on top of the Ethernet header) that VLAN requires.*/
|
|---|
| 577 |
|
|---|
| 578 | #define RTL8153_MAX_PACKET 9216 /* 9K */
|
|---|
| 579 | #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
|
|---|
| 580 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
|
|---|
| 581 | #define RTL8153_RMS RTL8153_MAX_PACKET
|
|---|
| 582 | #define RTL8152_TX_TIMEOUT (5 * HZ)
|
|---|
| 583 |
|
|---|
| 584 | #define MCU_TYPE_PLA 0x0100
|
|---|
| 585 | #define MCU_TYPE_USB 0x0000
|
|---|
| 586 |
|
|---|
| 587 | #define BYTE_EN_DWORD 0xff
|
|---|
| 588 | #define BYTE_EN_WORD 0x33
|
|---|
| 589 | #define BYTE_EN_BYTE 0x11
|
|---|
| 590 | #define BYTE_EN_SIX_BYTES 0x3f
|
|---|
| 591 | #define BYTE_EN_START_MASK 0x0f
|
|---|
| 592 | #define BYTE_EN_END_MASK 0xf0
|
|---|
| 593 | /* End new entries */
|
|---|
| 594 |
|
|---|
| 595 |
|
|---|
| 596 | #define GET_MII(sc) uether_getmii(&(sc)->sc_ue)
|
|---|
| 597 |
|
|---|
| 598 | struct rtl_intrpkt {
|
|---|
| 599 | uint8_t rtl_tsr;
|
|---|
| 600 | uint8_t rtl_rsr;
|
|---|
| 601 | uint8_t rtl_gep_msr;
|
|---|
| 602 | uint8_t rtl_waksr;
|
|---|
| 603 | uint8_t rtl_txok_cnt;
|
|---|
| 604 | uint8_t rtl_rxlost_cnt;
|
|---|
| 605 | uint8_t rtl_crcerr_cnt;
|
|---|
| 606 | uint8_t rtl_col_cnt;
|
|---|
| 607 | } __packed;
|
|---|
| 608 |
|
|---|
| 609 | struct rx_desc {
|
|---|
| 610 | uint32_t opts1;
|
|---|
| 611 | #define RX_LEN_MASK 0x7fff
|
|---|
| 612 |
|
|---|
| 613 | uint32_t opts2;
|
|---|
| 614 | #define RD_UDP_CS (1 << 23)
|
|---|
| 615 | #define RD_TCP_CS (1 << 22)
|
|---|
| 616 | #define RD_IPV6_CS (1 << 20)
|
|---|
| 617 | #define RD_IPV4_CS (1 << 19)
|
|---|
| 618 |
|
|---|
| 619 | uint32_t opts3;
|
|---|
| 620 | #define IPF (1 << 23) /* IP checksum fail */
|
|---|
| 621 | #define UDPF (1 << 22) /* UDP checksum fail */
|
|---|
| 622 | #define TCPF (1 << 21) /* TCP checksum fail */
|
|---|
| 623 | #define RX_VLAN_TAG (1 << 16)
|
|---|
| 624 |
|
|---|
| 625 | uint32_t opts4;
|
|---|
| 626 | uint32_t opts5;
|
|---|
| 627 | uint32_t opts6;
|
|---|
| 628 | };
|
|---|
| 629 |
|
|---|
| 630 | struct tx_desc {
|
|---|
| 631 | uint32_t opts1;
|
|---|
| 632 | #define TX_FS (1 << 31) /* First segment of a packet */
|
|---|
| 633 | #define TX_LS (1 << 30) /* Final segment of a packet */
|
|---|
| 634 | #define GTSENDV4 (1 << 28)
|
|---|
| 635 | #define GTSENDV6 (1 << 27)
|
|---|
| 636 | #define GTTCPHO_SHIFT 18
|
|---|
| 637 | #define GTTCPHO_MAX 0x7fU
|
|---|
| 638 | #define TX_LEN_MAX 0x3ffffU
|
|---|
| 639 |
|
|---|
| 640 | uint32_t opts2;
|
|---|
| 641 | #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
|
|---|
| 642 | #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
|
|---|
| 643 | #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
|
|---|
| 644 | #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
|
|---|
| 645 | #define MSS_SHIFT 17
|
|---|
| 646 | #define MSS_MAX 0x7ffU
|
|---|
| 647 | #define TCPHO_SHIFT 17
|
|---|
| 648 | #define TCPHO_MAX 0x7ffU
|
|---|
| 649 | #define TX_VLAN_TAG (1 << 16)
|
|---|
| 650 | };
|
|---|
| 651 |
|
|---|
| 652 |
|
|---|
| 653 | enum {
|
|---|
| 654 | RTL_BULK_DT_RD,
|
|---|
| 655 | RTL_BULK_DT_WR,
|
|---|
| 656 | RTL_INTR_DT_RD,
|
|---|
| 657 | RTL_N_TRANSFER,
|
|---|
| 658 | };
|
|---|
| 659 |
|
|---|
| 660 | enum {
|
|---|
| 661 | RTL_VER_UNKNOWN,
|
|---|
| 662 | RTL_VER_01,
|
|---|
| 663 | RTL_VER_02,
|
|---|
| 664 | RTL_VER_03,
|
|---|
| 665 | RTL_VER_04,
|
|---|
| 666 | RTL_VER_05,
|
|---|
| 667 | RTL_VER_MAX
|
|---|
| 668 | };
|
|---|
| 669 |
|
|---|
| 670 | struct rtl_softc {
|
|---|
| 671 | struct usb_ether sc_ue;
|
|---|
| 672 | struct mtx sc_mtx;
|
|---|
| 673 | struct usb_xfer *sc_xfer[RTL_N_TRANSFER];
|
|---|
| 674 |
|
|---|
| 675 | //TODO: If this the right place for this variable?
|
|---|
| 676 | uint16_t ocp_base;
|
|---|
| 677 | uint16_t version;
|
|---|
| 678 | uint32_t saved_wolopts;
|
|---|
| 679 |
|
|---|
| 680 | int sc_flags;
|
|---|
| 681 | #define RTL_FLAG_LINK 0x0001
|
|---|
| 682 | };
|
|---|
| 683 |
|
|---|
| 684 | #define RTL_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
|
|---|
| 685 | #define RTL_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
|
|---|
| 686 | #define RTL_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t)
|
|---|
