source: freebsd-rtl-driver/if_rtlreg.h@ 422

/*-

 * Copyright (c) 2010, 2011 Rick van der Zwet <info@rickvanderzwet.nl>

 *

 * Permission to use, copy, modify, and distribute this software for any

 * purpose with or without fee is hereby granted, provided that the above

 * copyright notice and this permission notice appear in all copies.

 *

 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF

 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES

 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN

 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF

 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

 */



/*-

 * Copyright (c) 2001-2003, Shunsuke Akiyama <akiyama@FreeBSD.org>.

 * All rights reserved.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in the

 *    documentation and/or other materials provided with the distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND

 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE

 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY

 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF

 * SUCH DAMAGE.

 *

 * $FreeBSD: release/10.1.0/sys/dev/usb/net/if_rtlreg.h 215335 2010-11-15 06:04:25Z kevlo $

 */



#define RTL_CONFIG_IDX          0       /* config number 1 */

#define RTL_IFACE_IDX           0



#define RTL_INTR_PKTLEN         0x8



#define RTL_TIMEOUT             50

#define RTL_MIN_FRAMELEN        60



/* Registers. */

#define RTL_IDR0                0x0120

#define RTL_IDR1                0x0121

#define RTL_IDR2                0x0122

#define RTL_IDR3                0x0123

#define RTL_IDR4                0x0124

#define RTL_IDR5                0x0125



#define RTL_MAR0                0x0126

#define RTL_MAR1                0x0127

#define RTL_MAR2                0x0128

#define RTL_MAR3                0x0129

#define RTL_MAR4                0x012A

#define RTL_MAR5                0x012B

#define RTL_MAR6                0x012C

#define RTL_MAR7                0x012D



#define RTL_CR                  0x012E  /* B, R/W */

#define RTL_CR_SOFT_RST         0x10

#define RTL_CR_RE               0x08

#define RTL_CR_TE               0x04

#define RTL_CR_EP3CLREN         0x02



#define RTL_TCR                 0x012F  /* B, R/W */

#define RTL_TCR_TXRR1           0x80

#define RTL_TCR_TXRR0           0x40

#define RTL_TCR_IFG1            0x10

#define RTL_TCR_IFG0            0x08

#define RTL_TCR_NOCRC           0x01

#define RTL_TCR_CONFIG          (RTL_TCR_TXRR1 | RTL_TCR_TXRR0 |        \

                                    RTL_TCR_IFG1 | RTL_TCR_IFG0)



#define RTL_RCR                 0x0130  /* W, R/W */

#define RTL_RCR_TAIL            0x80

#define RTL_RCR_AER             0x40

#define RTL_RCR_AR              0x20

#define RTL_RCR_AM              0x10

#define RTL_RCR_AB              0x08

#define RTL_RCR_AD              0x04

#define RTL_RCR_AAM             0x02

#define RTL_RCR_AAP             0x01

#define RTL_RCR_CONFIG          (RTL_RCR_TAIL | RTL_RCR_AD)



#define RTL_TSR                 0x0132

#define RTL_RSR                 0x0133

#define RTL_CON0                0x0135

#define RTL_CON1                0x0136

#define RTL_MSR                 0x0137

#define RTL_PHYADD              0x0138

#define RTL_PHYDAT              0x0139



#define RTL_PHYCNT              0x013B  /* B, R/W */

#define RTL_PHYCNT_PHYOWN       0x40

#define RTL_PHYCNT_RWCR         0x20



#define RTL_GPPC                0x013D

#define RTL_WAKECNT             0x013E



#define RTL_BMCR                0x0140

#define RTL_BMCR_SPD_SET        0x2000

#define RTL_BMCR_DUPLEX         0x0100



#define RTL_BMSR                0x0142



#define RTL_ANAR                0x0144  /* W, R/W */

#define RTL_ANAR_PAUSE          0x0400



#define RTL_ANLP                0x0146  /* W, R/O */

#define RTL_ANLP_PAUSE          0x0400



#define RTL_AER                 0x0148



#define RTL_NWAYT               0x014A

#define RTL_CSCR                0x014C



#define RTL_CRC0                0x014E

#define RTL_CRC1                0x0150

#define RTL_CRC2                0x0152

#define RTL_CRC3                0x0154

#define RTL_CRC4                0x0156



#define RTL_BYTEMASK0           0x0158

#define RTL_BYTEMASK1           0x0160

#define RTL_BYTEMASK2           0x0168

#define RTL_BYTEMASK3           0x0170

#define RTL_BYTEMASK4           0x0178



#define RTL_PHY1                0x0180

#define RTL_PHY2                0x0184



#define RTL_TW1                 0x0186



#define RTL_REG_MIN             0x0120

#define RTL_REG_MAX             0x0189



/* EEPROM address declarations. */

#define RTL_EEPROM_BASE         0x1200

#define RTL_EEPROM_IDR0         (RTL_EEPROM_BASE + 0x02)

#define RTL_EEPROM_IDR1         (RTL_EEPROM_BASE + 0x03)

#define RTL_EEPROM_IDR2         (RTL_EEPROM_BASE + 0x03)

#define RTL_EEPROM_IDR3         (RTL_EEPROM_BASE + 0x03)

#define RTL_EEPROM_IDR4         (RTL_EEPROM_BASE + 0x03)

#define RTL_EEPROM_IDR5         (RTL_EEPROM_BASE + 0x03)

#define RTL_EEPROM_INTERVAL     (RTL_EEPROM_BASE + 0x17)



#define RTL_RXSTAT_VALID        (0x01 << 12)

#define RTL_RXSTAT_RUNT         (0x02 << 12)

#define RTL_RXSTAT_PMATCH       (0x04 << 12)

#define RTL_RXSTAT_MCAST        (0x08 << 12)



/* New entries (imported from r8152.c) */

#define R8152_PHY_ID            32



#define PLA_IDR                 0xc000

#define PLA_RCR                 0xc010

#define PLA_RMS                 0xc016

#define PLA_RXFIFO_CTRL0        0xc0a0

#define PLA_RXFIFO_CTRL1        0xc0a4

#define PLA_RXFIFO_CTRL2        0xc0a8

#define PLA_FMC                 0xc0b4

#define PLA_CFG_WOL             0xc0b6

#define PLA_TEREDO_CFG          0xc0bc

#define PLA_MAR                 0xcd00

#define PLA_BACKUP              0xd000

#define PAL_BDC_CR              0xd1a0

#define PLA_TEREDO_TIMER        0xd2cc

#define PLA_REALWOW_TIMER       0xd2e8

#define PLA_LEDSEL              0xdd90

#define PLA_LED_FEATURE         0xdd92

#define PLA_PHYAR               0xde00

#define PLA_BOOT_CTRL           0xe004

#define PLA_GPHY_INTR_IMR       0xe022

#define PLA_EEE_CR              0xe040

#define PLA_EEEP_CR             0xe080

#define PLA_MAC_PWR_CTRL        0xe0c0

#define PLA_MAC_PWR_CTRL2       0xe0ca

#define PLA_MAC_PWR_CTRL3       0xe0cc

#define PLA_MAC_PWR_CTRL4       0xe0ce

#define PLA_WDT6_CTRL           0xe428

#define PLA_TCR0                0xe610

#define PLA_TCR1                0xe612

#define PLA_MTPS                0xe615

#define PLA_TXFIFO_CTRL         0xe618

#define PLA_RSTTALLY            0xe800

#define PLA_CR                  0xe813

#define PLA_CRWECR              0xe81c

#define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */

#define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */

#define PLA_CONFIG5             0xe822

#define PLA_PHY_PWR             0xe84c

#define PLA_OOB_CTRL            0xe84f

#define PLA_CPCR                0xe854

#define PLA_MISC_0              0xe858

#define PLA_MISC_1              0xe85a

#define PLA_OCP_GPHY_BASE       0xe86c

#define PLA_TALLYCNT            0xe890

#define PLA_SFF_STS_7           0xe8de

#define PLA_PHYSTATUS           0xe908

#define PLA_BP_BA               0xfc26

#define PLA_BP_0                0xfc28

#define PLA_BP_1                0xfc2a

#define PLA_BP_2                0xfc2c

#define PLA_BP_3                0xfc2e

#define PLA_BP_4                0xfc30

#define PLA_BP_5                0xfc32

#define PLA_BP_6                0xfc34

#define PLA_BP_7                0xfc36

#define PLA_BP_EN               0xfc38



#define USB_U2P3_CTRL           0xb460

#define USB_DEV_STAT            0xb808

#define USB_USB_CTRL            0xd406

#define USB_PHY_CTRL            0xd408

#define USB_TX_AGG              0xd40a

#define USB_RX_BUF_TH           0xd40c

#define USB_USB_TIMER           0xd428

#define USB_RX_EARLY_AGG        0xd42c

#define USB_PM_CTRL_STATUS      0xd432

#define USB_TX_DMA              0xd434

#define USB_TOLERANCE           0xd490

#define USB_LPM_CTRL            0xd41a

#define USB_UPS_CTRL            0xd800

#define USB_MISC_0              0xd81a

#define USB_POWER_CUT           0xd80a

#define USB_AFE_CTRL2           0xd824

#define USB_WDT11_CTRL          0xe43c

#define USB_BP_BA               0xfc26

#define USB_BP_0                0xfc28

#define USB_BP_1                0xfc2a

#define USB_BP_2                0xfc2c

#define USB_BP_3                0xfc2e

#define USB_BP_4                0xfc30

#define USB_BP_5                0xfc32

#define USB_BP_6                0xfc34

#define USB_BP_7                0xfc36

#define USB_BP_EN               0xfc38



/* OCP Registers */

#define OCP_ALDPS_CONFIG        0x2010

#define OCP_EEE_CONFIG1         0x2080

#define OCP_EEE_CONFIG2         0x2092

#define OCP_EEE_CONFIG3         0x2094

#define OCP_BASE_MII            0xa400

#define OCP_EEE_AR              0xa41a

#define OCP_EEE_DATA            0xa41c

#define OCP_PHY_STATUS          0xa420

#define OCP_POWER_CFG           0xa430

#define OCP_EEE_CFG             0xa432

#define OCP_SRAM_ADDR           0xa436

#define OCP_SRAM_DATA           0xa438

#define OCP_DOWN_SPEED          0xa442

#define OCP_EEE_ABLE            0xa5c4

#define OCP_EEE_ADV             0xa5d0

#define OCP_EEE_LPABLE          0xa5d2

#define OCP_ADC_CFG             0xbc06



/* SRAM Register */

#define SRAM_LPF_CFG            0x8012

#define SRAM_10M_AMP1           0x8080

#define SRAM_10M_AMP2           0x8082

#define SRAM_IMPEDANCE          0x8084



/* PLA_RCR */

#define RCR_AAP                 0x00000001

#define RCR_APM                 0x00000002

#define RCR_AM                  0x00000004

#define RCR_AB                  0x00000008

#define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)



/* PLA_RXFIFO_CTRL0 */

#define RXFIFO_THR1_NORMAL      0x00080002

#define RXFIFO_THR1_OOB         0x01800003



/* PLA_RXFIFO_CTRL1 */

#define RXFIFO_THR2_FULL        0x00000060

#define RXFIFO_THR2_HIGH        0x00000038

#define RXFIFO_THR2_OOB         0x0000004a

#define RXFIFO_THR2_NORMAL      0x00a0



/* PLA_RXFIFO_CTRL2 */

#define RXFIFO_THR3_FULL        0x00000078

#define RXFIFO_THR3_HIGH        0x00000048

#define RXFIFO_THR3_OOB         0x0000005a

#define RXFIFO_THR3_NORMAL      0x0110



/* PLA_TXFIFO_CTRL */

#define TXFIFO_THR_NORMAL       0x00400008

#define TXFIFO_THR_NORMAL2      0x01000008



/* PLA_FMC */

#define FMC_FCR_MCU_EN          0x0001



/* PLA_EEEP_CR */

#define EEEP_CR_EEEP_TX         0x0002



/* PLA_WDT6_CTRL */

#define WDT6_SET_MODE           0x0010



/* PLA_TCR0 */

#define TCR0_TX_EMPTY           0x0800

#define TCR0_AUTO_FIFO          0x0080



/* PLA_TCR1 */

#define VERSION_MASK            0x7cf0



/* PLA_MTPS */

#define MTPS_JUMBO              (12 * 1024 / 64)

#define MTPS_DEFAULT            (6 * 1024 / 64)



/* PLA_RSTTALLY */

#define TALLY_RESET             0x0001



/* PLA_CR */

#define CR_RST                  0x10

#define CR_RE                   0x08

#define CR_TE                   0x04



/* PLA_CRWECR */

#define CRWECR_NORAML           0x00

#define CRWECR_CONFIG           0xc0



/* PLA_OOB_CTRL */

#define NOW_IS_OOB              0x80

#define TXFIFO_EMPTY            0x20

#define RXFIFO_EMPTY            0x10

#define LINK_LIST_READY         0x02

#define DIS_MCU_CLROOB          0x01

#define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)



/* PLA_MISC_1 */

#define RXDY_GATED_EN           0x0008



/* PLA_SFF_STS_7 */

#define RE_INIT_LL              0x8000

#define MCU_BORW_EN             0x4000



/* PLA_CPCR */

#define CPCR_RX_VLAN            0x0040



/* PLA_CFG_WOL */

#define MAGIC_EN                0x0001



/* PLA_TEREDO_CFG */

#define TEREDO_SEL              0x8000

#define TEREDO_WAKE_MASK        0x7f00

#define TEREDO_RS_EVENT_MASK    0x00fe

#define OOB_TEREDO_EN           0x0001



/* PAL_BDC_CR */

#define ALDPS_PROXY_MODE        0x0001



/* PLA_CONFIG34 */

#define LINK_ON_WAKE_EN         0x0010

#define LINK_OFF_WAKE_EN        0x0008



/* PLA_CONFIG5 */

#define BWF_EN                  0x0040

#define MWF_EN                  0x0020

#define UWF_EN                  0x0010

#define LAN_WAKE_EN             0x0002



/* PLA_LED_FEATURE */

#define LED_MODE_MASK           0x0700



/* PLA_PHY_PWR */

#define TX_10M_IDLE_EN          0x0080

#define PFM_PWM_SWITCH          0x0040



/* PLA_MAC_PWR_CTRL */

#define D3_CLK_GATED_EN         0x00004000

#define MCU_CLK_RATIO           0x07010f07

#define MCU_CLK_RATIO_MASK      0x0f0f0f0f

#define ALDPS_SPDWN_RATIO       0x0f87



/* PLA_MAC_PWR_CTRL2 */

#define EEE_SPDWN_RATIO         0x8007



/* PLA_MAC_PWR_CTRL3 */

#define PKT_AVAIL_SPDWN_EN      0x0100

#define SUSPEND_SPDWN_EN        0x0004

#define U1U2_SPDWN_EN           0x0002

#define L1_SPDWN_EN             0x0001



/* PLA_MAC_PWR_CTRL4 */

#define PWRSAVE_SPDWN_EN        0x1000

#define RXDV_SPDWN_EN           0x0800

#define TX10MIDLE_EN            0x0100

#define TP100_SPDWN_EN          0x0020

#define TP500_SPDWN_EN          0x0010

#define TP1000_SPDWN_EN         0x0008

#define EEE_SPDWN_EN            0x0001



/* PLA_GPHY_INTR_IMR */

#define GPHY_STS_MSK            0x0001

#define SPEED_DOWN_MSK          0x0002

#define SPDWN_RXDV_MSK          0x0004

#define SPDWN_LINKCHG_MSK       0x0008



/* PLA_PHYAR */

#define PHYAR_FLAG              0x80000000



/* PLA_EEE_CR */

#define EEE_RX_EN               0x0001

#define EEE_TX_EN               0x0002



/* PLA_BOOT_CTRL */

#define AUTOLOAD_DONE           0x0002



/* USB_DEV_STAT */

#define STAT_SPEED_MASK         0x0006

#define STAT_SPEED_HIGH         0x0000

#define STAT_SPEED_FULL         0x0002



/* USB_TX_AGG */

#define TX_AGG_MAX_THRESHOLD    0x03



/* USB_RX_BUF_TH */

#define RX_THR_SUPPER           0x0c350180

#define RX_THR_HIGH             0x7a120180

#define RX_THR_SLOW             0xffff0180



/* USB_TX_DMA */

#define TEST_MODE_DISABLE       0x00000001

#define TX_SIZE_ADJUST1         0x00000100



/* USB_UPS_CTRL */

#define POWER_CUT               0x0100



/* USB_PM_CTRL_STATUS */

#define RESUME_INDICATE         0x0001



/* USB_USB_CTRL */

#define RX_AGG_DISABLE          0x0010



/* USB_U2P3_CTRL */

#define U2P3_ENABLE             0x0001



/* USB_POWER_CUT */

#define PWR_EN                  0x0001

#define PHASE2_EN               0x0008



/* USB_MISC_0 */

#define PCUT_STATUS             0x0001



/* USB_RX_EARLY_AGG */

#define EARLY_AGG_SUPPER        0x0e832981

#define EARLY_AGG_HIGH          0x0e837a12

#define EARLY_AGG_SLOW          0x0e83ffff



/* USB_WDT11_CTRL */

#define TIMER11_EN              0x0001



/* USB_LPM_CTRL */

#define LPM_TIMER_MASK          0x0c

#define LPM_TIMER_500MS         0x04    /* 500 ms */

#define LPM_TIMER_500US         0x0c    /* 500 us */



/* USB_AFE_CTRL2 */

#define SEN_VAL_MASK            0xf800

#define SEN_VAL_NORMAL          0xa000

#define SEL_RXIDLE              0x0100



/* OCP_ALDPS_CONFIG */

#define ENPWRSAVE               0x8000

#define ENPDNPS                 0x0200

#define LINKENA                 0x0100

#define DIS_SDSAVE              0x0010



/* OCP_PHY_STATUS */

#define PHY_STAT_MASK           0x0007

#define PHY_STAT_LAN_ON         3

#define PHY_STAT_PWRDN          5



/* OCP_POWER_CFG */

#define EEE_CLKDIV_EN           0x8000

#define EN_ALDPS                0x0004

#define EN_10M_PLLOFF           0x0001



/* OCP_EEE_CONFIG1 */

#define RG_TXLPI_MSK_HFDUP      0x8000

#define RG_MATCLR_EN            0x4000

#define EEE_10_CAP              0x2000

#define EEE_NWAY_EN             0x1000

#define TX_QUIET_EN             0x0200

#define RX_QUIET_EN             0x0100

#define sd_rise_time_mask       0x0070

#define sd_rise_time(x)         (min(x, 7) << 4)        /* bit 4 ~ 6 */

#define RG_RXLPI_MSK_HFDUP      0x0008

#define SDFALLTIME              0x0007  /* bit 0 ~ 2 */



/* OCP_EEE_CONFIG2 */

#define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */

#define RG_DACQUIET_EN          0x0400

#define RG_LDVQUIET_EN          0x0200

#define RG_CKRSEL               0x0020

#define RG_EEEPRG_EN            0x0010



/* OCP_EEE_CONFIG3 */

#define fast_snr_mask           0xff80

#define fast_snr(x)             (min(x, 0x1ff) << 7)    /* bit 7 ~ 15 */

#define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */

#define MSK_PH                  0x0006  /* bit 0 ~ 3 */



/* OCP_EEE_AR */

/* bit[15:14] function */

#define FUN_ADDR                0x0000

#define FUN_DATA                0x4000

/* bit[4:0] device addr */



/* OCP_EEE_CFG */

#define CTAP_SHORT_EN           0x0040

#define EEE10_EN                0x0010



/* OCP_DOWN_SPEED */

#define EN_10M_BGOFF            0x0080



/* OCP_ADC_CFG */

#define CKADSEL_L               0x0100

#define ADC_EN                  0x0080

#define EN_EMI_L                0x0040



/* SRAM_LPF_CFG */

#define LPF_AUTO_TUNE           0x8000



/* SRAM_10M_AMP1 */

#define GDAC_IB_UPALL           0x0008



/* SRAM_10M_AMP2 */

#define AMP_DN                  0x0200



/* SRAM_IMPEDANCE */

#define RX_DRIVING_MASK         0x6000



enum rtl_register_content {

        _1000bps        = 0x10,

        _100bps         = 0x08,

        _10bps          = 0x04,

        LINK_STATUS     = 0x02,

        FULL_DUP        = 0x01,

};



#define RTL8152_MAX_TX          4

#define RTL8152_MAX_RX          10

#define INTBUFSIZE              2

#define CRC_SIZE                4

#define TX_ALIGN                4

#define RX_ALIGN                8



#define INTR_LINK               0x0004



#define RTL8152_REQT_READ       0xc0

#define RTL8152_REQT_WRITE      0x40

#define RTL8152_REQ_GET_REGS    0x05

#define RTL8152_REQ_SET_REGS    0x05



#define BYTE_EN_DWORD           0xff

#define BYTE_EN_WORD            0x33

#define BYTE_EN_BYTE            0x11

#define BYTE_EN_SIX_BYTES       0x3f

#define BYTE_EN_START_MASK      0x0f

#define BYTE_EN_END_MASK        0xf0



#define VLAN_ETH_FRAME_LEN      1518    /* Max. octets in frame sans FCS */

#define VLAN_HLEN               4       /* The additional bytes (on top of the Ethernet header) that VLAN requires.*/



#define RTL8153_MAX_PACKET      9216 /* 9K */

#define RTL8153_MAX_MTU         (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)

#define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + VLAN_HLEN)

#define RTL8153_RMS             RTL8153_MAX_PACKET

#define RTL8152_TX_TIMEOUT      (5 * HZ)



#define MCU_TYPE_PLA            0x0100

#define MCU_TYPE_USB            0x0000



#define BYTE_EN_DWORD           0xff

#define BYTE_EN_WORD            0x33

#define BYTE_EN_BYTE            0x11

#define BYTE_EN_SIX_BYTES       0x3f

#define BYTE_EN_START_MASK      0x0f

#define BYTE_EN_END_MASK        0xf0

/* End new entries */





#define GET_MII(sc)             uether_getmii(&(sc)->sc_ue)



struct rtl_intrpkt {

        uint8_t rtl_tsr;

        uint8_t rtl_rsr;

        uint8_t rtl_gep_msr;

        uint8_t rtl_waksr;

        uint8_t rtl_txok_cnt;

        uint8_t rtl_rxlost_cnt;

        uint8_t rtl_crcerr_cnt;

        uint8_t rtl_col_cnt;

} __packed;



struct rx_desc {

        uint32_t opts1;

#define RX_LEN_MASK                     0x7fff



        uint32_t opts2;

#define RD_UDP_CS                       (1 << 23)

#define RD_TCP_CS                       (1 << 22)

#define RD_IPV6_CS                      (1 << 20)

#define RD_IPV4_CS                      (1 << 19)



        uint32_t opts3;

#define IPF                             (1 << 23) /* IP checksum fail */

#define UDPF                            (1 << 22) /* UDP checksum fail */

#define TCPF                            (1 << 21) /* TCP checksum fail */

#define RX_VLAN_TAG                     (1 << 16)



        uint32_t opts4;

        uint32_t opts5;

        uint32_t opts6;

};



struct tx_desc {

        uint32_t opts1;

#define TX_FS                   (1 << 31) /* First segment of a packet */

#define TX_LS                   (1 << 30) /* Final segment of a packet */

#define GTSENDV4                (1 << 28)

#define GTSENDV6                (1 << 27)

#define GTTCPHO_SHIFT           18

#define GTTCPHO_MAX             0x7fU

#define TX_LEN_MAX              0x3ffffU



        uint32_t opts2;

#define UDP_CS                  (1 << 31) /* Calculate UDP/IP checksum */

#define TCP_CS                  (1 << 30) /* Calculate TCP/IP checksum */

#define IPV4_CS                 (1 << 29) /* Calculate IPv4 checksum */

#define IPV6_CS                 (1 << 28) /* Calculate IPv6 checksum */

#define MSS_SHIFT               17

#define MSS_MAX                 0x7ffU

#define TCPHO_SHIFT             17

#define TCPHO_MAX               0x7ffU

#define TX_VLAN_TAG                     (1 << 16)

};





enum {

        RTL_BULK_DT_RD,

        RTL_BULK_DT_WR,

        RTL_INTR_DT_RD,

        RTL_N_TRANSFER,

};



enum {

        RTL_VER_UNKNOWN,

        RTL_VER_01,

        RTL_VER_02,

        RTL_VER_03,

        RTL_VER_04,

        RTL_VER_05,

        RTL_VER_MAX

};



struct rtl_softc {

        struct usb_ether        sc_ue;

        struct mtx              sc_mtx;

        struct usb_xfer *sc_xfer[RTL_N_TRANSFER];



        //TODO: If this the right place for this variable?

        uint16_t                ocp_base;

        uint16_t                version;

        uint32_t                saved_wolopts;

        

        int                     sc_flags;

#define RTL_FLAG_LINK           0x0001

};



#define RTL_LOCK(_sc)           mtx_lock(&(_sc)->sc_mtx)

#define RTL_UNLOCK(_sc)         mtx_unlock(&(_sc)->sc_mtx)

#define RTL_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t)