1 | /* Author : Rick van der Zwet
|
---|
2 | * S-number : 0433373
|
---|
3 | * Version : $Id: datapath.c 365 2007-12-03 08:54:04Z rick $
|
---|
4 | * Copyright : FreeBSD Licence
|
---|
5 | * Description : Memory unit
|
---|
6 | */
|
---|
7 |
|
---|
8 | #include <stdlib.h>
|
---|
9 | #include <stdio.h>
|
---|
10 | #include <sysexits.h>
|
---|
11 | #include "datapath.h"
|
---|
12 | #include "imm.h"
|
---|
13 | #include "constant.h"
|
---|
14 | #include "memory.h"
|
---|
15 |
|
---|
16 | word
|
---|
17 | select_sx(const sx_control_t control)
|
---|
18 | {
|
---|
19 | word out=0;
|
---|
20 | switch (control)
|
---|
21 | {
|
---|
22 | case NO_COMPONENT:
|
---|
23 | out = 0;
|
---|
24 | break;
|
---|
25 | case A:
|
---|
26 | out = a;
|
---|
27 | break;
|
---|
28 | case B:
|
---|
29 | out = b;
|
---|
30 | break;
|
---|
31 | case TEMP:
|
---|
32 | out = temp;
|
---|
33 | break;
|
---|
34 | case TEMP2:
|
---|
35 | out = temp2;
|
---|
36 | break;
|
---|
37 | case PC:
|
---|
38 | out = pc;
|
---|
39 | break;
|
---|
40 | case MAR:
|
---|
41 | out = mar;
|
---|
42 | break;
|
---|
43 | case MDR:
|
---|
44 | out = mdr;
|
---|
45 | break;
|
---|
46 | case CONST:
|
---|
47 | out = constant;
|
---|
48 | break;
|
---|
49 | case IMM:
|
---|
50 | out = imm;
|
---|
51 | break;
|
---|
52 | default:
|
---|
53 | fprintf(stderr, "Switch '%i' not implemented\n", control);
|
---|
54 | exit(EX_SOFTWARE);
|
---|
55 | break;
|
---|
56 | };
|
---|
57 | return (out);
|
---|
58 | }
|
---|
59 |
|
---|
60 | void
|
---|
61 | update_state(control_t control)
|
---|
62 | {
|
---|
63 | word temp_destbus;
|
---|
64 | word temp_mem;
|
---|
65 |
|
---|
66 | constant = constant_call(control.constant);
|
---|
67 | imm = imm_call(ir, control.ir);
|
---|
68 |
|
---|
69 | /* Going to ALU if activated */
|
---|
70 | word in1 = 0;
|
---|
71 | word in2 = 0;
|
---|
72 | if (control.alu_unit == ALU_STALLED) {
|
---|
73 | temp_destbus = 0;
|
---|
74 | } else {
|
---|
75 | in1 = select_sx(control.s1);
|
---|
76 | in2 = select_sx(control.s2);
|
---|
77 | temp_destbus = alu(in1, in2, control.alu_unit);
|
---|
78 | }
|
---|
79 |
|
---|
80 | if (control.c == WRITE)
|
---|
81 | c = temp_destbus;
|
---|
82 | if (control.temp == WRITE)
|
---|
83 | temp = temp_destbus;
|
---|
84 | if (control.temp2 == WRITE)
|
---|
85 | temp2 = temp_destbus;
|
---|
86 | if (control.pc == WRITE)
|
---|
87 | pc = temp_destbus;
|
---|
88 | if (control.mar == WRITE)
|
---|
89 | mar = temp_destbus;
|
---|
90 | if (control.mdr == WRITE) {
|
---|
91 | if (control.mux == DATAPATH)
|
---|
92 | mdr = temp_destbus;
|
---|
93 | else if (control.mux == MEMORY)
|
---|
94 | mdr = temp_mem;
|
---|
95 | else {
|
---|
96 | fprintf(stderr, "Mux control not defined\n");
|
---|
97 | exit(EX_SOFTWARE);
|
---|
98 | }
|
---|
99 | }
|
---|
100 |
|
---|
101 | /* Memory actions */
|
---|
102 | if (control.memory != MEM_STALLED) {
|
---|
103 | mem_busy = TRUE;
|
---|
104 | temp_mem = mem_operation(mar, mdr, control.memory);
|
---|
105 | if (control.ir == WRITE)
|
---|
106 | ir = temp_mem;
|
---|
107 | if (control.mdr == WRITE && control.mux == MEMORY)
|
---|
108 | mdr = temp_mem;
|
---|
109 | }
|
---|
110 |
|
---|
111 |
|
---|
112 | /* Register actions */
|
---|
113 | if (control.a == WRITE && ((control.reg & 1) != 0))
|
---|
114 | a = reg[control.register_address_a];
|
---|
115 | if (control.b == WRITE && ((control.reg & 2) != 0))
|
---|
116 | b = reg[control.register_address_b];
|
---|
117 | if ((control.reg & 4) != 0)
|
---|
118 | reg[control.register_address_c] = c;
|
---|
119 | }
|
---|